Hardware Acceleration: Traders and Teraflops 
Author:  Kevin McPartland 
Date:   6/16/2009 
Price: US $ 3,000.00 

Hardware Acceleration:
Traders and Teraflops

Executive Summary
Despite the obvious co-dependence between hardware and software, a debate has raged since the first punch card as to whose work provides greater performance improvement: that of the software developer or that of the hardware engineer. Is it tightly written code that reduces execution-algorithm latency, or is it the use of the latest and greatest chip that makes the difference?

In the same vein, hardware acceleration is often viewed as an all-or-nothing proposition: You either believe that algorithms and market data handlers run faster on specialty chips, or you dismiss the idea as a passing fad that would ultimately be supplanted by better and faster CPUs from Intel and AMD. Though there will always be proponents of one proposition over the other, the debate has outlived its usefulness: We now know that a specially crafted combination of traditional and hardware-accelerated software is what yields optimal results.

Like all other things low latency, cutting microseconds (µs) isn’t necessary for every business approach.  But at firms whose trading strategies don’t depend on the lowest possible latency, the idea of reducing space and power costs by moving from a rack of servers to a single hardware-accelerated appliance will have traders, CFOs and CTOs cheering. Luckily there is no need to choose one option or the other.  Traditional software, CPUs, programmable chips and hardware-accelerated appliances all have their places in the financial services data center. We just need to teach them all how to get along.

Today’s college graduates will come to Wall Street knowing how parallel programming works, and knowing how to apply it to real business problems.  Hardware acceleration will not be a chosen path or an afterthought; it will be a natural part of the development process. So as multicore chips expand from four to eight cores, many-core chips grow from 240 to 480 cores, and programmable chips add millions of logic devices, existing code will already be written to exploit the increasingly parallel architectures.

Data rates will not stop growing and latency will not stop dropping. As we work our way out of the last few years and into a new world of trading and investment banking, financial firms will need innovative technology more than ever in order to remain competitive and win. Tools are critical, but it is the approach that must be well understood: After all, software cannot be developed and improved upon unless we grasp exactly where and how it will run.

For all of our talk about hardware acceleration, the truth is that “hardware acceleration” will be an archaic term before we know it—not because the tools will have gone away, but because the concepts will be so embedded in the software development lifecycle they will not require a separate name. Power and smarts have met, and the rubber is finally meeting the road.

The TABB Group Vision Note on Hardware Accleration:
Traders and Teraflops

This Vision Note is based on conversations with financial markets participants including trading firms, execution venues and solutions providers.  The report defines hardware acceleration beyond specialty chips, outlines key considerations for selecting the approach most appropriate for a given project and lays out the future of hardware acceleration.




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